In recent years, as the scale of a semiconductor logic circuit has become large, the number of test input patterns required to test such a semiconductor integrated circuit has become great. However, such a semiconductor logic circuit has a limited storage capacity for storing test input patterns to be used in a system test which is to be executed after such a semiconductor integrated circuit is built into a system, or a field test or the like which is to be executed after shipping. In order to solve such a problem, it is important to provide high fault coverage with a small amount of data to be stored.
Here, description will be made regarding a semiconductor integrated circuit to be tested. In many cases, typical semiconductor logic circuits are each configured as a sequential circuit. Such a sequential circuit includes a combinational circuit portion comprising logic elements such as AND gates, NAND gates, OR gates, NOR gates, and the like, and flip-flops (FF) configured to store the internal state of the circuit. In this case, such a combinational circuit portion includes primary input lines (PI), pseudo primary input lines (PPI) each configured as an output line of a corresponding flip-flop, primary output lines (PO), and pseudo primary output lines (PPO) each configured as an input line of a corresponding flip-flop. In an input operation in which a signal is input to the combinational circuit portion, a part of the input operation is performed directly via a primary input line, and the other part of the input operation is performed indirectly via a pseudo primary input line. Furthermore, in an output operation in which a signal is output from the combinational circuit portion, a part of the output operation is performed directly via a primary output line, and the other part of the output operation is performed indirectly via a pseudo primary output line.
In order to test such a combinational circuit portion included in the sequential circuit, there is a need to input a predetermined test input pattern via such primary input lines and pseudo primary input lines of the combinational circuit portion, and to acquire a test response signal from the combinational circuit portion via the primary output lines and the pseudo primary output lines.
However, with such a sequential circuit, typically, it is not possible for an external circuit to directly access the output lines of the flip-flops (pseudo primary input lines) and the input lines (pseudo primary output lines) of the flip-flops. Thus, a test for such a combinational circuit requires controllability of the pseudo primary input lines, and requires observability of the pseudo primary output lines, which is a problem.
As a major method for solving such a problem of controllability and observability in the combinational circuit portion test, a full scan method based on a full scan design is known. With such a full scan design, the flip-flops are each configured as a scan flip-flop, and a single or multiple scan chains are formed using the scan flip-flops. The operation of each scan flip-flop is controlled via a corresponding scan enable (SE) signal line. For example, when SE=0, the flip-flop performs the same operation as that of a conventional flip-flop. In this state, upon receiving a clock pulse, the output value of the scan flip-flop is set to the value output from the combinational circuit portion, thereby updating the output value of the scan flip-flop. On the other hand, when SE=1, the scan flip-flop forms a single shift register together with the other scan flip-flops included in the same scan chain. In this state, upon receiving a clock pulse, an updated value received from the outside is scanned in to the scan flip-flop. At the same time, a value held by the scan flip-flop is scanned out to outside the flip-flop. Typically, the scan flip-flops included in the same scan chain are configured to share a common scan enable signal line. It should be noted that, in some cases, different scan chains share a single scan enable line. Otherwise, such different scan chains have different respective scan enable signal lines.
Referring to FIG. 14, further description will be made regarding a conventional scan test. FIG. 14 is a diagram showing a test cycle of a scan test.
A test for a combinational circuit portion of a full scan sequential circuit is performed by repeatedly executing a scan shift operation and a scan capture operation. The scan shift operation is performed in a shift mode in which SE=1. In the shift mode, one or multiple clock pulses are supplied, and one or multiple updated values are scanned in from the outside to the scan flip-flops included within the scan chain. Furthermore, at the same time, one or multiple values held by the scan flip-flops included within the scan chain are scanned out to the outside. The scan capture operation is performed in the capture mode in which SE=0. In the capture mode, a single clock pulse is supplied at the same time to all the scan flip-flops included within the scan chain, and the values output via the pseudo primary output lines of the combinational circuit portion are acquired and held by all the scan flip-flops.
The scan shift operation is used to input a test input pattern to the combinational circuit portion via the pseudo primary input lines, and to acquire a test response signal from the combinational circuit portion via the pseudo primary output lines. On the other hand, the scan capture operation is used for the scan flip-flops to acquire and hold a test response from the combinational circuit portion. Such a scan shift operation and such a scan capture operation are repeatedly performed for all the test input patterns, thereby allowing the combinational circuit portion to be tested.
Next, referring to FIG. 15, description will be made regarding fault detection using a conventional scan test. FIG. 15 is a block diagram showing a fault detection system 101 using a background technique of the present invention.
The fault detection system 101 includes an acquisition apparatus 107, a judgment apparatus 111, and a pattern control apparatus 113. The acquisition apparatus 107 includes an acquisition unit 117 and a storage unit 121. The judgment apparatus 111 includes a comparison unit 129 and a fault judgment unit 131. The pattern control apparatus 113 includes a test input pattern holding unit 133, an expanding circuit 135, and a compressing circuit 137.
With the scan test method, a part of the test input pattern input operation is performed directly via a primary input port, and the other part of the test input pattern input operation is performed indirectly via the scan shift operation. Such a scan shift operation allows a desired logic value to be set for a desired scan flip-flop, thereby solving a problem of controllability of the pseudo primary input lines. Moreover, a part of the test response acquisition from the combinational circuit portion 3 is performed directly via a primary output port, and the other part of the test response acquisition is performed indirectly via the scan shift operation. The scan shift operation allows the acquisition unit 117 to acquire the output value of a desired scan flip-flop, thereby solving a problem of observability of the pseudo primary output lines. It should be noted that, typically, the number of scan flip-flops is the same as the number of pseudo primary output lines. The comparison unit 129 compares the acquired values with the values predicted for when the combinational circuit portion 3 operates normally. The fault judgment unit 131 judges based on the judgment result whether or not there is a fault in the combinational circuit portion 3.
Typically, in a case of performing a system test or a field test for such a semiconductor integrated circuit, built-in self-test (BIST) is performed. In particular, the GIST has a problem of a limited storage capacity for storing a test input pattern. Thus, various techniques have been developed for reducing the amount of test data.
Examples of such a method include a method in which a test input pattern is compressed, and the compressed test input pattern is used as a seed pattern (seed). The seed is expanded before a scan-in operation. Furthermore, a seed is obtained by compression and scan-out operation. Thus, such an arrangement allows the amount of test data to be reduced. However, as the scale of semiconductor integrated circuits has become large, there has been an increased demand for a technique for further reducing the amount of test data.
Now, referring to FIGS. 16 and 17, description will be made regarding a multiple capture method described in Non-patent document 1. The multiple capture method is employed to maintain the fault coverage even if the partial scan design is employed. FIG. 16 is a diagram showing a test cycle using the multiple capture method. FIG. 17 is a flowchart showing a procedure in a case of employing a conventional multiple capture method.
With such a partial scan design, the number of flip-flops designed as the scan flip-flops is reduced, thereby reducing the circuit size. However, such an arrangement has a problem in that the input logic value cannot be set for flip-flops that were not designed as scan flip-flops. With such an arrangement, the acquired logic values provide insufficient information with respect to a fault, leading to a problem of reduced fault coverage.
In order to solve the aforementioned problem, with the multiple capture method, as shown in FIG. 16, the capture operation is repeatedly performed multiple times for each test input pattern in a capture mode. That is to say, the logic value acquired by each flip-flop 5 shown in FIG. 5 is input to the combinational circuit portion 3 as an updated input test pattern. With such an arrangement, the values captured by the respective flip-flops 5 are sequentially set in an incremental manner. Finally, the logic values are set for all the flip-flops 5. Thus, such an arrangement allows a set test output pattern to be obtained according to the set test input pattern. As a result, such an arrangement allows the fault coverage to be maintained even for a partial scan design semiconductor integrated circuit.
Specific description will be made with reference to FIG. 17 regarding a procedure for detecting a fault using the fault detection system 101. The input of a seed is started (Step ST501), and the seed is expanded by the expanding circuit 135 (Step ST502). The shift mode is started (Step ST503), and the test input pattern is scanned in to the flip-flops 5 (Step ST504). Subsequently, the capture mode is started (Step ST505), and the capture operation is repeatedly performed a predetermined number of times (ST506). In this step, the values of the test input pattern are sequentially set in an incremental manner every time the capture operation is repeatedly performed. The shift mode is again started (Step ST507), and the logic values held by the flip-flops 5 are scanned out (Step ST508). Next, when there is any remaining seed that has not been input, the flow returns to Step ST501. Otherwise, the flow proceeds to the next step (Step ST509). The acquisition unit 117 acquires the compressed data (signature) that is scanned out (Step ST510). The comparison unit 129 compares the signature thus obtained with a signature predicted for when the combinational circuit portion 3 operates normally (Step ST511). The fault judgment unit 131 judges based on the comparison result whether or not the combinational circuit portion 3 has a fault (Step ST512).